Modern semiconductor fabrication processes are well developed. The excellent technologies of semiconductor processes make the applications of integrated circuits widespread increasingly. People's most electronic products adopt integrated circuits as the core device for controlling the electronic products. Thanks to semiconductor processes, the area of integrated circuits is smaller increasingly, which makes the sizes of the electronic products, such as MP3 players, notebook computers, and digital cameras, smaller accordingly. Because of fine and delicate semiconductor processes, thousands of chips can be fabricated on a wafer. In addition, because the integrated circuit chips are very small, testers cannot perform testing by naked eyes or hands. Consequently, many testing equipments and methods are developed nowadays for testing integrated circuit chips. For example, the pad test of integrated circuit chips performs test on the pads used for wiring in integrated circuit chips. Thereby, the integrated circuit chips with malfunctioning pads will not be packaged and shipped, products with flaws will be avoided, and the brand images of the manufacturing firms of the integrated circuits can be enhanced.
FIG. 1 and FIG. 2 show schematic diagrams of multi-pads test in integrated circuits by a testing apparatus according to the prior art. As shown in the figures, the method of multi-pads test in integrated circuits according to the prior art adopts a testing port 102, wherein a plurality of testing probes 104 are set (as shown in FIG. 3), installed in a testing apparatus 10. The testing apparatus 10 is set in a testing machine (not shown in the figures) with a wafer 20 under test loaded therein. The wafer 20 comprises a plurality of integrated circuit chips 22. When the testing machine tests the integrated circuit chips 22 of the wafer 20, the wafer 20 is moved. Thereby, each integrated circuit chip 22 of the wafer 20 can be aligned with the testing port 102 of the testing apparatus 10 sequentially for the testing probes 104 of the testing port 102 to couple with each of the pads 222 on the integrated circuit chip 22, respectively.
The testing apparatus 10 can transmit a testing signal to the pads 222 of the integrated circuit chip 22 via the plurality of testing probes 104 and to testing circuits 224, respectively. Thereby, by detecting the output signal of an output terminal 226 of the testing circuit 224 in the integrated circuit chip 22, whether the pad 222 can transmit signals normally can be known. That is, by inputting testing signals to the pads 222, when the output signals are detected in the output terminals 226, it means that the integrated circuit chip 22 can transmit signals normally, the test is passed, and the pads 222 of the integrated circuit chip 22 can function normally. When the plurality of pads 222 and the plurality of testing circuits 224 maintain normal electrical coupling, the output terminals 226 of the integrated circuit chip 22 can output the output signals corresponding to the testing signals, which means the plurality of pads 222 functions normally. On the contrary, when one of the plurality of output terminals 226 corresponding to the plurality of pads 222 cannot output signals, it means that one of the plurality of pads 222 operates abnormally. Thereby, whether the pads 222 of the integrated circuit chip 22 function normally can be tested.
However, given the semiconductor fabrication processes are finer increasingly, the number of pads increases accordingly. Besides, in order to maximize productivity by increasing number of integrated circuit chips in a fixed area, the size of pads becomes smaller and denser. Because the number of testing probes of the testing apparatus according to the prior art needs to be equal to the number of pads in a single integrated circuit chip, the number of testing probes of the testing apparatus according to the prior art has to increase and the distribution of the pads had to be denser as well for corresponding to the locations of the pads. As a result, the circuit of the testing apparatus becomes more complicated, making the design of the testing apparatus difficult. Furthermore, an increase in the density of the testing probes results in a raise in the cost of the testing apparatus.
Accordingly, the present invention provides a circuit for multi-pads test, which not only can improve the drawbacks of traditional pad testing by decreasing the number of the testing probes, but also can enhance the reliability of pad testing.